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JESD204B Intel® FPGA IP Blueprint Example User Guide: Intel® Quartus® Prime Standard Edition
i.vii.8.3. Software Interrupt Service Routines (ISR)
In this blueprint example, the post-obit peripherals have their IRQ output ports connected to the IRQ input port of the Nios Two processor:
- JESD204B IP core TX base layer
- JESD204B IP core RX base layer
- SPI chief
- Timer
- Reset sequencer
The software C code included as part of the design example defines the ISRs for the following peripherals:
- JESD204B IP core TX base layer
- JESD204B IP core RX base layer
- SPI master
The ISRs in the C code is a basic routine that performs two tasks:
- Clear IRQ error flag
- Print mistake blazon and message (for JESD204B IP core TX and RX base layer ISR only)
Error types and messages printed past the JESD204B IP core TX base layer ISR:
- SYNC_N error
- SYSREF LMFC mistake
- DLL data invalid mistake
- Ship layer information invalid error
- SYNC_N link reinitialization request
- Transceiver PLL locked error
- Phase compensation FIFO full error
- Phase compensation FIFO empty mistake
Error types and messages printed by the JESD204B IP cadre RX base layer ISR:
- SYSREF LMFC error
- DLL data ready error
- Ship layer data ready error
- Lane deskew error
- RX locked to data mistake
- Phase compensation FIFO full error
- Phase compensation FIFO empty mistake
- Code group synchronization error
- Frame alignment error
- Lane alignment mistake
- Unexpected One thousand graphic symbol
- Non in tabular array error
- Running disparity error
- Initial Lane Alignment Sequence (ILAS) error
- DLL error reserve condition
- ECC mistake corrected
- ECC fault fatal
The mistake types correspond to the tx_err, rx_err0, and rx_err1 status registers in the JESD204B IP core TX and RX register maps respectively. The PRINT_INTERRUPT_MESSAGES parameter in the main.h header file controls the printing of interrupt mistake letters in the Nios 2 console window. Ready the parameter to 1 (default) to print error messages, else set to 0. Refer to the Software Parameters section for more details. You tin can modify the ISRs in the C code to customize the interrupt handling response based on your system specifications.
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Source: https://www.intel.com/content/www/us/en/docs/programmable/683094/22-1/software-interrupt-service-routines-isr.html
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